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Integrated Circuit Systems, Inc.
ICS9DB106 Preliminary Product Preview
6 Output PCI Express* Buffer with CLKREQ# Function
Recommended Application: 1-to-6 Zero-delay or fanout buffer for PCI Express Output Features: * 6 - 0.7V current mode differential output pairs (HSCL) * SMBus for complete device control Key Specifications: * Cycle-to-cycle jitter < 40ps * Output-to-output skew < 30 ps Features/Benefits: * CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications * PLL or bypass mode/PLL can dejitter incoming clock * Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's * Spread Spectrum Compatible/tracks spreading input clock for low EMI * SMBus Interface/unused outputs can be disabled Pin Configuration
PLL_BW 1 28 VDDA CLK_INT 2 27 GNDA CLK_INC 3 26 IREF *CLKREQ1# 4 25 **CLKREQ4# PCIEXT0 5 24 PCIEXT5 PCIEXC0 6 23 PCIEXC5 VDD 7 22 VDD GND 8 21 GND PCIEXT1 9 20 PCIEXT4 PCIEXC1 10 19 PCIEXC4 PCIEXT2 11 18 PCIEXT3 PCIEXC2 12 17 PCIEXC3 VDD 13 16 VDD SMBDAT 14 15 SMBCLK Note: Pins preceeded by '**' have internal 120K ohm pull down resistors
28-pin SSOP & TSSOP
0833A--07/26/04
*Other names and brands may be claimed as the property of others.
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9DB106
Integrated Circuit Systems, Inc.
ICS9DB106 Preliminary Product Preview
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN NAME PLL_BW CLK_INT CLK_INC **CLKREQ1# PCIEXT0 PCIEXC0 VDD GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 VDD SMBDAT SMBCLK VDD PCIEXC3 PCIEXT3 PCIEXC4 PCIEXT4 GND VDD PCIEXC5 PCIEXT5 **CLKREQ4# PIN TYPE IN IN IN IN OUT OUT PWR IN OUT OUT OUT OUT PWR I/O IN PWR OUT OUT OUT OUT PWR PWR OUT OUT IN DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high "True" reference clock input. "Complimentary" reference clock input. Output enable for PCI Express output pair '1' 0 = enabled, 1 = tri-stated True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Output enable for PCI Express output pair '4' 0 = enabled, 1 = tri-stated This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
26 27 28
IREF GNDA VDDA
OUT PWR PWR
Note: Pins preceeded by '**' have internal 120K ohm pull down resistors
0833A--07/26/04
2
Integrated Circuit Systems, Inc.
ICS9DB106 Preliminary Product Preview
General Description
The ICS9DB106 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB106 is driven by a differential SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the ICS9DB106 suitable for Express Card applications.
Block Diagram
CLKREQ1# CLKREQ4#
PCIEX1 CLK_INT SPREAD COMPATIBLE PLL PCIEX4
C LK_INC
PLL_BW SMBDAT SMBCLK CONTROL LOGIC
PCIEX(0,2,3,5)
IREF
Power Groups
Pin Number VDD GND 7, 13, 16, 22 8,21 TBD TBD N/A 27 28 27 Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core
0833A--07/26/04
3
Integrated Circuit Systems, Inc.
ICS9DB106 Preliminary Product Preview
Absolute Max
Symbol VDDA VDD Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Output Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Operating Supply Current Input Frequency Pin Inductance Input Capacitance Clk Stabilization Input Spread Spectrum Modulation Frequency SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time
1
CONDITIONS 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance From VDD reaching 3.1V and input clock stable Triangular Modulation
MIN 2 VSS - 0.3 -5 -5 -200
TYP
MAX VDD + 0.3 0.8 5
UNITS Notes V V uA uA uA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
I DD3.3OP Fi Lpin CIN COUT TSTAB
99
130 30 100
150 40 101 7 5 4.5 1.8
mA mA MHz nH pF pF ms kHz V V mA
30 2.7
33 5.5 0.4
VDD VOL IPULLUP TRI2C TFI2C
@ IPULLUP 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15)
1000 300
ns ns
Guaranteed by design and characterization, not 100% tested in production.
0833A--07/26/04
4
Integrated Circuit Systems, Inc.
ICS9DB106 Preliminary Product Preview
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Outputs
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2 , RP=49.9 REF 9, PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Input to Output Delay Duty Cycle Output-to-Output Skew Jitter, Cycle to cycle
1 2
SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-tf tpd tpdbyp dt3 tsk3 tjcyc-cyc
CONDITIONS VO = V x Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V V OH = 0.525V VOL = 0.175V
MIN 3000 660 -150 -300 250
TYP
MAX
UNITS
NOTES 1 1,3
850 mV 150 1150 550 140 mV mV mV ppm ns ns ns ps ps ps ps ps ns % ps ps ps
1,3 1,3 1,3 1,3 1,3 1,2 2 2 1,2 1 1 1 1 1 1 1 1 1 1
9.9970 9.9970 9.8720 175 175
0 10.0030 10.0533 700 700 125 125 150 3.7 55 30 40 25
PLL Mode. Bypass mode Measurement from differential wavefrom VT = 50% PLL mode, Measurement from differential wavefrom BYPASS mode as additive jitter
100 3.2 45
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements I REF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .
3
0833A--07/26/04
5
Integrated Circuit Systems, Inc.
ICS9DB106 Preliminary Product Preview
SMBusTable: Device Control Register, READ/WRITE ADDRESS (DC/DD) Byte 0 0 1 PWD Pin # Name Control Function Type PLL controlled Enables SMBus PLL controlled SW_EN RW by SMBus 1 Bit 7 Control by device pins registers RW X RESERVED Bit 6 RW X RESERVED Bit 5 RW X RESERVED Bit 4 RESERVED RW X Bit 3 RESERVED RW X Bit 2 Selects PLL PLL BW #adjust RW Low BW High BW 1 Bit 1 Bandwidth Bypasses PLL for PLL bypassed PLL enabled 1 PLL Enable RW Bit 0 (fan out mode) (ZDB mode) board test SMBusTable: Output Enable Register Pin # Name Control Function Type Byte 1 RESERVED RW Bit 7 RW RESERVED Bit 6 PCIEX5 Output Control RW 24,23 Bit 5 RW RESERVED Bit 4 PCIEX3 Output Control RW 18,17 Bit 3 PCIEX2 Output Control RW 11,12 Bit 2 RW RESERVED Bit 1 PCIEX0 Output Control RW 5,6 Bit 0 SMBusTable: Function Select Register Pin # Name Control Function Type Byte 2 RW RESERVED Bit 7 RW RESERVED Bit 6 RESERVED RW Bit 5 RW RESERVED Bit 4 RW RESERVED Bit 3 RESERVED RW Bit 2 RESERVED RW Bit 1 RESERVED RW Bit 0
0 Disable Disable Disable Disable
1
Enable Enable Enable Enable
PWD X X 1 X 1 1 X 1
0 -
1
PWD X X X X X X X X
0833A--07/26/04
6
Integrated Circuit Systems, Inc.
ICS9DB106 Preliminary Product Preview
SMBusTable: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type RID3 R Bit 7 RID2 R Bit 6 REVISION ID RID1 R Bit 5 RID0 R Bit 4 VID3 R Bit 3 VID2 R Bit 2 VENDOR ID VID1 R Bit 1 VID0 R Bit 0 SMBusTable: DEVICE ID Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 -
1 -
PWD X X X X 0 0 0 1
Name
Control Function Type R R R Device ID R = 06 Hex R R R R
0 -
1
PWD 0 0 0 0 0 1 1 0
SMBusTable: Byte Count Register Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 1 1 0
0833A--07/26/04
7
Integrated Circuit Systems, Inc.
ICS9DB106 Preliminary Product Preview
209 mil SSOP SYMBOL A A1 A2 b c D E E1 e L N a VARIATIONS N 28 D mm. MIN 9.90 MAX 10.50 MIN .390 D (inch) MAX .413 In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0 8
Reference Doc.: JEDEC Publication 95, MO-150
10-0033
Ordering Information
ICS9DB106yFLF-T
Example:
ICS XXXX y F LF-T
Designation for tape and reel packaging Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0833A--07/26/04
8
Integrated Circuit Systems, Inc.
ICS9DB106 Preliminary Product Preview
N
c
4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil)
L
(25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
SYMBOL A A1 A2 b c D E E1 e L N a aaa VARIATIONS N 28
INDEX AREA
E1
E
12 D
A2 A1
A
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
-Ce
b SEATING PLANE
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS9DB106yGLF-T
Example:
ICS XXXX yG LF-T
Designation for tape and reel packaging Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0833A--07/26/04
9

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